Taiwanese chip foundry TSMC has unveiled its N12e process technology for IoT applications in the 5G and AI era.

The technology now in risk production is optimised for edge AI applications by providing powerful computing performance and power efficiency.

It brings TSMC’s FinFET transistor technology to edge devices enhanced with ultra-low leakage (ULL) devices and SRAM to deliver more than 1.75 times logic density improvement, and approximately 1.5 times performance improvement or less than half of the power consumption of the prior 22ULL technology generation.

An enhancement of the 12FFC+ process, N12e is suitable for AI-enabled IoT devices, giving them ample power to perform functions such as understanding natural speech or image classification while improving power efficiency. N12e also cuts the power cord and makes it possible to run powerful AI-enabled IoT devices on batteries.

TSMC showed these developments at the company’s first online technology symposium and open innovation ecosystem forum last month. TSMC brought its largest annual events online to maintain this connection with customers and ecosystem partners during the global pandemic.

More than 5000 people registered for virtual events designed for North America, Europe, Japan, Taiwan and China.

“During these difficult times for communities around the world, people are relying on technology to communicate with and to comfort each other,” said CC Wei, CEO of TSMC. “Our customer’s innovations make the world a smarter and more connected place. TSMC is committed to unleashing our customer’s innovations with the most advanced logic technologies, a full portfolio of specialty processes to bridge the physical and digital world, advanced packaging technologies, and a comprehensive set of system integration solutions.”

Also announced was that the 5nm N5 technology entered volume production this year and defect density reduction is proceeding faster than the previous generation as capacity continues to ramp. N5 provides a 15% performance gain or a 30% power reduction, and up to 80% logic density gain over the preceding N7 technology. Building on the original N5, TSMC plans to ramp an enhanced N5P version in 2021, offering an additional 5% speed gain and 10% power improvement.

TSMC also offered a preview of the latest member of the 5nm family – the N4 process. N4 will provide improvements in performance, power and density to cover a wide range of products. In addition to process simplification with reduced mask layers, N4 also offers a straightforward migration path with the ability to leverage the comprehensive 5nm design ecosystem. The N4 process is scheduled to start risk production in the fourth quarter of 2021, with volume production in 2022.

Looking ahead to the next generation, TSMC’s N3 process is on track to become what the company hopes will be the most advanced logic technology in the world featuring up to 15% performance gain, up to 30% power reduction, and a logic density gain up to 70% over N5.

In addition, TSMC introduced 3DFabric, an umbrella of the company’s portfolio of 3DIC system integration under one family of technologies that offer flexibility for creating systems through robust chip interconnections. With an array of options for both silicon stacking at the front end and packaging chips together at the back end, 3DFabric enables users to connect logic dies together, to high-bandwidth memory or to heterogeneous chiplets such as analogue, IO and RF blocks.

What’s more, 3DFabric is the industry’s first product capable of combining back-end 3D and front-end 3D technologies for a multiplier effect in system integration. It augments and complements transistor scaling for continuously improving system performance, functionality, slimming down form factors and improving time to market.