Renesas designs 32bit Risc-V core for IoT

  • December 6, 2023
  • Steve Rogerson

Japanese electronics company Renesas has designed a 32bit CPU core based on the open-standard Risc-V instruction set architecture (ISA), providing an open and flexible platform for IoT, consumer electronics, healthcare and industrial systems.

The Risc-V CPU core will complement Renesas’ existing IP portfolio of 32bit microcontrollers (MCUs), including the proprietary RX and RA families based on the Arm Cortex-M architecture.

Risc-V is an open ISA that is quickly gaining popularity in the semiconductor industry, due to its flexibility, scalability, power efficiency and open ecosystem. While many MCU providers have recently created joint investment alliances to accelerate their development of Risc-V products, Renesas has already developed a Risc-V core on its own.

This CPU can serve as a main application controller, a complementary secondary core in SoCs, on-chip subsystems, or even in deeply embedded ASSPs.

Renesas previously introduced 32bit voice-control and motor-control ASSP devices, as well as the RZ/Five 64bit general purpose microprocessors (MPUs), which were built on CPU cores developed by Taiwanese firm Andes Technology (

“Renesas takes pride in offering embedded processing for the broadest range of customers and applications,” said Daryl Khoo, vice president of Renesas’ IoT platform division. “This new core extends our leadership in the Risc-V market and uniquely positions us to deliver more solutions that accommodate a diverse range of requirements.”

Calista Redmond, CEO of Risc-V International, added: “We congratulate Renesas on achieving its recent milestone in 32bit Risc-V MCU architecture development. This achievement exemplifies how Risc-V ecosystem partners, such as Renesas, are rapidly advancing Risc-V innovation. Our Risc-V community now spans 70 countries with more than 4000 members, and we eagerly anticipate further innovations emerging from this dynamic, expanding market.”

The Renesas Risc-V CPU achieves a 3.27 CoreMark/MHz performance,. It includes extensions to improve performance, while reducing code size.

Renesas is sampling devices based on the core to select users, with plans to launch its first Risc-V-based MCU and associated development tools in Q1 2024. More information about Risc-V is available at